?2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6921MR Rev. 1.0.4
8
Electrical Characteristics (Continued)
V
DD
=15 V, T
A
=-40癈 ~105癈 (T
A
=T
J
), unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
PFC Stage
Voltage Error Amplifier Section
Gm
Transconductance
(4)
100
125
150
祄ho
V
REF
Feedback Comparator Reference
Voltage
2.465
2.500
2.535
V
V
INV-H
Clamp High Feedback Voltage
RANGE=Open
2.70
2.75
2.80
V
RANGE=Ground
2.60
2.65
2.70
V
RATIO
Clamp High Output Voltage Ratio
(4)
V
INVH
/ V
REF
,
RANGE=Open
1.06
1.14
V/V
V
INVH
/ V
REF
,
RANGE=Ground
1.04
1.08
V
INV-L
Clamp Low Feedback Voltage
2.25
2.35
2.45
V
V
INV-OVP
Over-Voltage Protection for INV
Input
RANGE=Open
2.90
2.95
V
RANGE=Ground
2.75
2.80
t
INV-OVP
Over-Voltage Protection Debounce
Time
50
70
90
祍
V
INV-UVP
Under-Voltage Protection for INV
Input
0.35
0.45
0.55
V
t
INV-UVP
Under-Voltage Protection
Debounce Time
50
70
90
祍
V
INV-BO
PWM and PFC Off Threshold for
Brownout Protection
1.15
1.20
1.25
V
V
COMP-BO
Limited Voltage on COMP Pin for
Brownout Protection
1.55
1.60
1.65
V
V
COMP
Comparator Output High Voltage
4.8
6.0
V
V
OZ
Zero Duty Cycle Voltage on COMP
Pin
1.10
1.25
1.40
V
I
COMP
Comparator Output Source
Current
V
INV
=2.3 V, V
COMP
=1.5 V
15
30
45
礎
V
INV
=1.5 V
0.50
0.75
1.00
mA
Comparator Output Sink Current
RANGE=Open,
V
INV
=2.75 V, V
COMP
=5 V
20
30
40
礎
RANGE=Ground,
V
INV
=2.65 V, V
COMP
=5 V
20
30
40
PFC Current Sense Section
V
CSPFC
Threshold Voltage for Peak
Current Cycle-by-Cycle Limit
V
COMP
=5 V
0.82
V
t
PD
Propagation Delay
110
200
ns
t
BNK
Leading-Edge Blanking Time
110
180
250
ns
A
V
CSPFC Compensation Ratio for
THD
0.90
0.95
1.00
V/V
Continued on the following page&
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